Disclaimer:
ANY INFORMATION IS PROVIDED AS IS, WITHOUT ANY WARRANTY ON WHATEVER YOU THINK.
EVERYTHING YOU DO, YOU DO IT AT YOUR OWN RISK UNDER YOUR RESPONSABILITY.
AUTHOR WILL NOT BE RESPONSIBLE FOR ANY DAMAGE, RELATED OR UNRELATED WITH WHAT’S REPORTED HERE.
Well, first of all I want to tell you than I’m beginner about VHDL & c. 🙂
I’m playing with XSA50 board, I have to make some experience, so I’m lurking for ready-to-use examples to better understand the whole thing.
On Xess website (http://www.xess.com) there area lots of examples, but few of them are for XSA50 board.
A little more are for XSA100 board, that is very similar to XSA50 except for:
-FPGA chip:XSA50 has XC2S50 FPGA, XSA100 has XC2S50 FPGA, both from Spartan2 family;
-SRAM chip: XSA50 has 8M-Byte chip, XSA100 has 16M-Byte chip.
You may find more infos on XSA board manual, more manuals here .
Well, XSA50 examples aren’t that popular, so XSA100 examples on Retromicro website are very usefull.
I started with “VGA Bouncing Ball on XSA-100 Board” (vgaBall) and “VGA Character Display on XSA-100 Board” (vgaChars) examples thinking they were easy … wrong! 😦
Getting .bit file at first run isn’t easy (to me was impossible).
These examples, and I think the other examples too, were made with Xilinx ISE 5.1 while Xilinx ISE 10.1 is now available.
Don’t you like it? 😉
I made some changes to different files in order to get .bit file compiled.
Please, first of all read documentation of each example.
READ CAREFULLY (better more than twice)
I’ve got .bit files but I haven’t tested yet, so I don’t know what those files really are. sorry
ANY INFORMATION IS PROVIDED AS IS, WITHOUT ANY WARRANTY ON WHATEVER YOU THINK.
EVERYTHING YOU DO, YOU DO AT YOUR OWN RISK UNDER YOUR RESPONSABILITY.
I WILL NOT BE RESPONSIBLE FOR ANY DAMAGE YOU’LL HAVE,RELATED OR UNRELATED INFORMATION PRESENT HERE
Here are the changes.
- file chipIO.ucf
- rename pin_dqmh and pin_dqml ports (line 78 and 79)
78: NET “pin_sdram_dqmh” LOC = “p124”;
79: NET “pin_sdram_dqml” LOC = “p122”;
- comment pin_rs232_rd as pin_rs232_cts assignments (lines 81 and 82), (they share pin with ps2 pins)
81: #NET “pin_rs232_rd” LOC = “p60”;
82: #NET “pin_rs232_cts” LOC = “p62”;
- rename pin_dqmh and pin_dqml ports (line 78 and 79)
54: — pin_rs232_rd : in std_logic; — receive data
55: pin_rs232_td : out std_logic; — transmit data
56: — pin_rs232_cts : in std_logic; — clear to send
8: -p xc2s50-6tq144
- change architecture parameter in ngdbuild and map commands
-p xc2s50-tq144-6
- (optional) add “-detail” parameter to map command
- change effort level parameter in map command
-ol high
- do it at your own risk!!!: add “-d” parameter to bitgen command in order to exclude DRC step (do it at your own risk!!!)
(once more…)
READ CAREFULLY (better more than twice)
I’ve got .bit files but I haven’t tested yet, so I don’t know what those files really are.
ANY INFORMATION IS PROVIDED AS IS, WITHOUT ANY WARRANTY ON WHATEVER YOU THINK.
EVERYTHING YOU DO, YOU DO AT YOUR OWN RISK UNDER YOUR RESPONSABILITY.
I WILL NOT BE RESPONSIBLE FOR ANY DAMAGE YOU’LL HAVE,RELATED OR UNRELATED INFORMATION PRESENT HERE
more: RetroMicro Examples, Xess examples
Technorati tags: XSA, VHDL, BIT